Tensilica Enhances Xtensa Configurable Processor Families
Portable Design News, Tuesday December 11, 2007
Tensilica, Inc. today announced that it has upgraded its two Xtensa configurable processor families (the Xtensa 7 and Xtensa LX2) with new hardware options and software tool enhancements that make it appeal to an even wider audience of SOC (system-on-chip) designers.
Highlights of these capabilities include a new, smaller general purpose register file option, new integer multiplier and divider execution unit options, two new AMBA (Advanced Microcontroller Bus Architecture 3.0) bridge options, as well as an easy-to-use new configuration tool that analyzes source C/C++ code and automatically suggests VLIW (very long instruction word) instruction extensions that lead to 30-60% improvements in general purpose code performance. These new capabilities provide designers with the most productive configurable processor design environment, with automated features that ensure that each processor design is correct by construction.
New Hardware Options
The five most significant new hardware options introduced by Tensilica include: a 16-entry register file, a relocatable exception vector option, a low-area multiplier, an integer divider, and new AMBA-compatible bridges.
First, Tensilica added support for a smaller 16-entry main register file in the Xtensa processor, in addition to the existing support for 32-entry and 64-entry configuration options. This enables the instantiation of a very small processor core that competes in area and power with 8-bit and 16-bit microcontrollers and yet provides the performance, flexibility, and features of a 32-bit controller.
Second, by adding support for relocatable exception vectors, Tensilica is enabling customers to change the memory location of exception and interrupt handlers in software post-silicon. This gives more flexibility to the SOC designer and eases system design.
Third, Tensilica added a low-area, multi-cycle 32x32 multiplier configuration option, which enables the design of an Xtensa configuration that is very small in area, but still has good performance on multiply-rich applications, such as MP3 decoding. This gives designers a new choice that is more area efficient than the existing single-cycle, fully-pipelined 32-bit and 16-bit multiplier configuration choices and still much higher performance than pure software emulation of multiply instructions.
Fourth, Tensilica added a low-area divider configuration option, requiring only about 4000 gates. This provides a standardized and powerful way to boost performance on numerically intensive applications such as those running on GPS (global positioning satellite) controllers and real-time control code applications that are typical of servo, motor and engine control.
Finally, Tensilica added the AMBA 3 AXI bridge as a click-box configuration option. This, in addition to the existing AMBA 2 AHB-lite (Advanced High-performance Bus-lite) bridge option, allows designers to seamlessly drop Xtensa processors into AMBA-based systems and eases the use of Xtensa processors with other AMBA peripherals.
All of these enhancements just started shipping with the November 2007 release of Xtensa LX2 and Xtensa 7 processor cores and the Tensilica software development tools.
Tensilica Inc., Santa Clara,CA (408) 986-8000 [www.tensilica.com]
